1. Field of the Invention
The present invention relates to an output voltage stabilization circuit, and more particularly, to an output voltage stabilization circuit of a display device driving circuit, which stabilizes an output voltage of the display device driving circuit.
2. Description of the Related Art
In general, an electric paper refers to a display device including a plurality of globular capsules and a plastic transistor arranged over and under the globular capsules. Unlike existing displays using backlights, the electric paper uses reflected light like paper.
An electric paper display device (EPD) has a production cost lower than existing flat display panels. Furthermore, since the EPD does not require backlights and continuous recharging, the EPD exhibits excellent energy efficiency. The EPD may offer a sharper image and a wider viewing angle than liquid crystal displays (LCD). Furthermore, since the EPD has a memory function, previous data stored therein is not lost although power is turned off. Therefore, the EPD may be widely used in bulletin boards, electronic books and so on.
In order for the EPD to maintain previous data, a driving circuit of the EPD should maintain an output at a ground level VSS after power off. In the conventional EPD, however, the output of the driving circuit may not be maintained at the ground level VSS depending on a power-off sequence.
FIG. 1 is a block diagram illustrating the configuration of a driving circuit of a conventional EPD.
Referring to FIG. 1, the driving circuit 100 of the conventional EPD includes a level shifter 110 and an output driver 120.
The level shifter 110 is configured to convert low voltage data LV DATA_1 to LV DATA_3 into high voltage data HV DATA_1 to HV DATA_3 using a low source voltage VCC, a high source voltage VPOS/VNEG, and a bias voltage Vbias_LV, and then provide the converted data to the output driver 120. The output driver 120 is configured to provide an output signal OUTPUT corresponding to the high voltage data HV DATA_1 to HV DATA_2 to a display panel (not illustrated). The output signal OUTPUT includes a ground voltage VSS and a high source voltage VPOS/VNEG.
The low source voltage VCC is a source voltage which is supplied to a low source voltage circuit for inputting a signal to the output driver 120. For example, the low source voltage circuit may include a circuit (not illustrated) for generating the bias voltage Vbias_LV or the level shifter 110 for generating the low voltage data LV DATA_1 to LV DATA_3. The high source voltage VPOS/VNEG is a source voltage supplied to the output driver 120. The high source voltage VPOS/VNEG includes a positive source voltage VPOS and a negative source voltage VNEG.
As illustrated in FIG. 1, the driving circuit of the EPD includes a low source voltage circuit using a low source voltage and a high source voltage circuit using a high source voltage. Among driving circuits, a general logic circuit operates at a low source voltage, and an output circuit for driving a display panel operates at a high source voltage.
FIG. 2 is a circuit diagram illustrating the output driver of FIG. 1.
Referring to FIG. 2, the output driver 120 is configured to selectively output the positive voltage VPOS, the negative voltage VNEG, or the ground voltage VSS according to the level of the high voltage data HV DATA_1 to HV DATA_3 provided from the level shifter 110.
The conventional EPD includes a low source voltage circuit using a low source voltage and a high source voltage circuit using a high source voltage different from the low source voltage. The circuits using two or more different source voltages in such a manner may malfunction depending on the power off sequence of the low source voltage and the high source voltage. Such a malfunction may have a fatal effect on the EPD.
FIG. 3 is a diagram illustrating a power off sequence when the low source voltage VCC is turned off before the high source voltage VPOS/VNEG in the driving circuit of the EPD.
Referring to FIG. 3, when the low source voltage VCC is first turned off, the level shifter 110 receives an abnormal signal and outputs an abnormal signal. Accordingly, the output driver 120 may output a signal at an ambiguous level, instead of the positive voltage VPOS, the negative voltage VNEG, or the ground voltage VSS.
That is, when the low source voltage VCC is turned off before the high source voltage VPOS/VNEG in the driving circuit of the EPD, the ambiguous-level output signal of the level shifter 110 is applied to an input terminal of the output driver 120, and the input terminal of the output driver 120 becomes in a floating state. Accordingly, an output terminal of the output driver 120 may also become in a floating state.
FIG. 4 is a diagram illustrating a power off sequence when the high source voltage VPOS/VNEG is turned off before the low source voltage VCC in the driving circuit of the EPD.
Referring to FIG. 4, when a strong light source is irradiated onto the EPD while the high source voltage VPOS/VNEG is turned off, a different result from a result based on an input of the level shifter 110 may be outputted due to a malfunction of the level shifter 110. Accordingly, the output driver 120 outputs a voltage at an unexpected level.